power
HPC and Data for Lattice QCD
power
NOTE: The order of power-up of the two crates within a rack is relevant:
* After long, i.e. >(10 min-2h), power of overload error (red LED)
* It may happen that one or more PB's remain in exception
The upper crate should be switched on before the lower crate (in general, the crate, which by it's root board feeds the clock to the other crates, should be switched-on first, in order to avoid the other crates running without clock)
happens frequently: - Often a very short power off (< 1sec) is enough to cure problem (i.e. switch on the PSU for >= 10 sec, if red LED "OL" does not turn green, switch off for just less than about 1 sec) - Otherwise try (dirty!) clock trick: remove clock input of root board, switch on machine, re-attach clock cable, press hard reset button of root board. - If completely desperate: detach the PCs and try power-on. If power-on still no possible detach 1-4 processing boards. After successful power-on wait for O(0.5h) before attaching PCs and PBs again.
after power up:
Sasha's Trick: Leave PSU on for a few minutes and than try power-off-on again (Explanation: Thermal effect of PSU)
Walter's Trick: Connect inhibit/OK signals of various PSU in such a way, that 3.3 V comes up before 5V (Explanation: On-chip exceptions)
There are actually two ways to do that: [Maurizio]
a) Clean:
- Resistor 10 k between Emitter of 3.3 V unit Ground.
and
- Connect Emitter of 3.3 V unit with Inhibit-Input of 5.5 V unit
b) Dirty:
Connect Inhibit-Output of 3.3V unit with Inhibit- Input of 5V unit
Delay Circuit [Neuricam]:
Generates inhibit for 5 V for O(few ms) after 3.3 V starts rising. Monitored by an oscilloscope, the net effect is that the 3.3 V lines reach a voltage level of about 0.5...1 V BEFORE the 5 V lines (although the 3.3 V lines reach their final nominal value O(20 ms) AFTER the 5 V lines)
Brute force (not recommended): Increase current limitation