Deutsches Elektronen-Synchrotron DESY
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| HPC and Data for Lattice QCD

rootboard

HPC and Data for Lattice QCD

rootboard

HOWTO load and change the configuration of the Root-Board

Structure of the RootBoard (new version):

The RootBoard hosts 6 Alteras, 1 Flex and 5 Max (PM7256)
The Flex implements the PCI interface and can be loaded
either via the serial connector P09/P10 (volatile, for testing)
or from the PROM (for permanent configuration).
The 5 Max implement the various levels of the Root hierarchy:
- APEunit 0 and 2
- APEunit 1 and 3
- APEcrate
- APEtower
- APEmaster (presently not used in order to shorten root latency)

Configuring the Max Altera's of the RootBoard

See also HOWTO-Altera
Files in directory /zroot/maxplus/Root7dic99_17may2000:
AggiornamentiPLDs/CPCI/Root/Root_17May2000_Rev214:
	cpci.pof -- Flex configuration for PROM
	cpci.sof -- Flex configuration via serial cable
Root1000_7Dic99:
	root7dic.jcf	-- Configuration of all Max via JTAG chain
	AU02.pof	-- Configuration of Max (Root of APEunit 0+2)
	au13.pof	-- Configuration of Max (Root of APEunit 1+3)
	cr.pof		-- Configuration of Max (Root of APEcrate)
	tr.pof		-- Configuration of Max (Root of APEtower)
	mr.pof		-- Configuration of Max (not used???)
	root7dic.acf	-- pin-out (irrelevant)
	root7dic.hif	-- irrelevant
Note: The file root7dic.jcf configures a JTAG chain which is then
used to upload the configuration of all the 5 Max Alteras. The
absolute path names must be adjusted according to the actual path
of the files!
The "verify" command is supposed to give an error when verifying
one of the last files (mr.pof???)

Configuring the Flex Altera's of the RootBoard

Usually the Flex takes its configuration at power-up from the
EPROM, which is presently configured with the file
/zroot/maxplus/Root7dic99_17may2000/AggiornamentiPLDs/CPCI/Root/Root_17May2000_Rev214/cpci.pof
During development tests, the Flex may also be loaded via JTAG
or an EPROM emulator (connectors P09 and P10). In this case, the
EPROM itself must be removed!
WARNING: This should only be done after power-up, such that the
PC can not see the PCI-device (NEVER after having already configured
the Flex)

Configuring the Programmable Logic (Altera) of the (old) Pisa-Rootboard

  - cpci: znpfiles:/mensh/altera/RootPisa/cpci.sof
  - au0 : ../au02.pof
  - au1 : ../au13.pof
  - cr  : ../cr.pof

Accessing Root Registers with caos

	printf hex mr_readpci 0xf  (=address/4)
	mr_writepci 0xf <value>

Masking un-used Unit's (or PB's???)

	testpci_c21.73

	  (s) - select target
		Vendor: 0xaaaa
		Device: 0x6666
		Index:	RETURN
		Function: RETURN
	  (e) - edit
		Base address:	0x40100000
		Address Offset:	0x24
		Data:		0x00ffffc0
			(masking all boards except unit 0 )
		Error messages because of different MSB can be ignored!

	/zroot/tools/rootmask 0xffffc0 --> mask all but unit 0
	/zroot/tools/rootmask 0xfff000 --> mask all but unit 0,1

Setting Clock Frequency:

Note: Clock is reset to default value by PCI-Reset (leaving
      value 0 in the register) and at power-on.

	testpci_c21.73
	  (s) - select target
		Vendor: 0xaaaa
		Device: 0x6666
		Index:	RETURN
		Function: RETURN
	  (e) - edit
		Base_address:	0x40100000
		Offset:		0x3c
		data:		0x700 (set 64 MHz)
				0x70b (set 66 MHz)-default
				0x713 (set 68 MHz)
				0x6f3 (set 60 MHz)

	/zroot/tools/rootclock 64