DM

Short for Data Memory.
Each Tmille and each Jmille have their own data memory.

Jmille, Jn

Jmille is the floating point processor of APEmille with support for arithmetic, logical and bitwise operations on complex, double precision, single precision and integer data types.
Eight of them are on each Processing Board. Each Jmille has its own Data Memory, the Program Memory is controlled by the Tmille processor.
Jn is shorthand for the inofficial nickname 'Jane'.

PB

Short for Processing Board or Processor Board.

Program Memory

The memory where the actual program code resides in.
On APEmille this is a separate memory module that controlled by

Tmille and distributed to itself and to all eight Jmille on the PB. There's no program cache on APEmille.

MAD

The MAD is the floating point processor of APE100/QUADRICS. It is a

VLIW,

pipelined,

synchronous,

single chip Cmos integrated

processor.
Its main characteristics are:

• peak power of 50 MFLOPS (at 25 MHz clock);
• single precision;
• optimized to execute the so called Normal Operations
• integrated EDAC (Error Detection and Correction);
• integrated LUT (Look Up Table) for operations like:
  1/X, 1/sqrt(X), ln X, exp(X)
• integrated logic for the local IF management;
• Register File (RF) for 128 words.

Each chip contains about 150,000 transistors in 81 mm2.
Its power consumption is about 1 watt.

Normal Operation

A floating point operation of the form

D = A x B + C

where the operands may be of type real, complex or

vector.
In principle one could define also integer normal operations, but none of the APE architectures implements this.

SIMD Architecture

SIMD = Single Instruction - Multiple Data
A parallel computer architecture where one single program image is run on all processing nodes and each of them executes the same instruction synchronously. Each node has it's own local memory however.

SPMD Architecture

SPMD = Single Program - Multiple Data
A parallel computer architecture where one single program image is run on all processing nodes but each of them is relatively free to alter the program flow. Here, synchronization between the processing elements is done explicitly.

Tmille, Tz

The central control processor on each Processing Board. Tz is short for the inofficial nickname 'Tarzan'.

Vector

Jmille knows a data type that can best be thought of as two real numbers treated in parallel.

VLIW Architecture

VLIW = Very Long Instruction Word
A computer architecture that reads instruction words that contain multiple instructions. If parallelism allows simultaneous execution of the multiple instructions, each instruction can be placed in a separate pipeline.
In the APEmille architecture a VLIW contains instructions for the integer (Tmille) and the floating point (Jmille) processing units.

ZCPU

The ZCPU is an integer processor, optimized to operate as the APE100/QUADRICS controller.
It is a

VLIW,

pipelined,

synchronous,

single chip Cmos integrated

processor.
Each chip contains about 120,000 transistors in 87 mm². Its power consumption is about 1 watt.