APEmode

HPC and Data for Lattice QCD

APEmode

The APEmode Control Bus (hs 3.10.2001)

The APEmode bus distributes low-level control signals between
PCI-Interface, ClockController and the Processors on the PB.
There exist the following (low-level) APEmode's:

	APEmode		APEmode Bus[3:0]
	---------------------------------
	System Mode	0 0 0 0
	Run Mode	0 0 0 1
	Remote Mode	0 0 1 0
	Reserved	0 0 1 1
	FSMReset	0 1 0 0
	GlbRootReset	0 1 0 1
	Partial Halt	0 1 1 0
	Full Halt	0 1 1 1
	Refresh 	1 X X 0
	Refresh Exit	1 X X 1

The bit APEmode Bus[4] is the Parity (even) bit.
To monitor the Refresh activity one can connect a signal analyser to the
Test-Points for CcApeMode or ChApeMode on the PB. The relevant signals
are APEmode[3] (TP4 or TP14) and APEmode[0] (TP10 or TP20).
The trigger conditions for monitoring the delay between 2 successive Refresh
cycles have been stored as "Setup5" on the APE Signal Analyser (by Piero Chiesa
on 3.10.2001). The following connections are assumed:

	Probe 1 --> ApeMode[1]
	Probe 2 --> ApeMode[2] (X)
	Probe 3 --> ApeMode[3] (X)
	Probe 4 --> ApeMode[4] (parity)
	Probe 5 --> ApeMode[0]

It triggers on the elapsed time between the two events:
1) Refresh Exit: Probes[5:1] = LHHLL (i.e. ApeMode[4:0] = 11000)
2) Refresh Start: Probes[5:1] = HLHLL (i.e. ApeMode[4:0] = 01001)