Each Processing Node is composed of a Jmille floating point processor, attached to a SDRAM local memory. The Memory Controller inside Jmille generates addresses for the External Memory summing up a Global Address given by Tmille and a Local Address computed by Jmille itself. This way each APEmille Processing Node is able to generate a different Memory Address. The five addresses needed by the Multiport Register File are fixed at compile time, and therefore distributed to Jmille inside the VLIW (Very Long Instruction Word).
Each Processing Node generates Status Signals (Global conditions, Exceptions etc.). These Status Signals are collected into a Global Status Return managed by the Control System on the Rootboard. This connection allows the Control System to execute flow control instructions based on simultaneous logical conditions produced by the set of Processing Nodes.
The instruction words read by Jmille specify the set of address locations inside the large multiport Register File of Jmille, and controls the ALU inside the processing node. Moreover it specifies Local Conditional Operations, Local Addressing functions, and Special Arithmetic functions calculations to be performed by Jmille.
