HPC
HPC

| HPC and Data for Lattice QCD

Root Board

HPC and Data for Lattice QCD

Root Board

Documentation

Patches

  • Patch A: Termination for PECL CLK (R27, R28)
  • Patch B: Use external clock
  • Patch C: Replace R374 for using clock generated by HIB
  • Patch D: Various terminations: R300, R105, R109, R125, R165, R153, R141, R201, R189, R177, R225, R213, R237, R273, R249, R261, R277

Configuration

rack modality

Modification of DIP switch S1 and S2 to distribute clock signal from master root board to slave root board. Master root board receives clock from HIB.

upper crate master root board                 lower crate slave root board
S1-1 on                                       S1-1 on
S1-2 on                                       S1-2 on
S1-3 on                                       S1-3 on
S1-4 on                                       S1-4 on

S2-1 off                                      S2-1 on
S2-2 off                                      S2-2 off
S2-3 on                                       S2-3 on
S2-4 on                                       S2-4 on

Clock cable from upper master board "Clk Out" to lower slave root board "Clk In".

nrun.conf should be checked, if change needed.