refresh
HPC and Data for Lattice QCD
refresh
Changing Refresh Rate:
Write value 0xRRDD into Altera Register 0x800 of PB (Refresh Control Register), where 0xRR is the refresh-free run time
in msec and 0xDD is the refresh duration in msec.
Default setting: 0x320a
Recommended setting: 0x2002 [Piero 8/2000]
Max setting within Memory specs (=64 ms): 0x4001 [Piero 21.9.2000]
Most aggressive setting: 0xff01 [Piero 21.9.2000]
Disabling Refresh:
Write value 0x8 into Altera Register 0x40 of PB (Configuration Register) or use
krun -a 0x8
Refresh Synchronisation between PBs:
The refresh activity is autonomously governed by each PB. Synchronisation of the refresh activity is to be guaranteed only by the syncronous resetting
of the PB's local refresh counters by the global control signals from the
RootBoard at transition to RUN-Mode.
In SYSTEM-Mode the refresh activities of the PBs are independent and asynchronous!
Monitoring Refresh:
By connecting a signal analyser to the test-points of the APEmode Bus onthe PB it is possible to monitor the refresh activity (see HOWTO-APEmode).
hs 8/8/2000