Compile
HPC and Data for Lattice QCD
Compile
apeNEXT compile chain HOWTO, October 2005 (author: Nils Christian)
To access the tools for compiling C or TAO code for apeNEXT, one first has to setup the apeNEXT environment. This is done by the following commands (here for [t]csh):setenv NROOT /afs/ifh.de/group/ape/nroot source $NROOT/nlogin.csh
1) Compiling C code
To compile C code the nlcc compiler is used:nlcc -S sourcefile.c
-S Instruct compiler to only generate high-level assembly -gp Inline source code into assembler as comment
Remarks:
At the moment there does not exist a linker, which means that you
have to combine your sources. Hint: Use cpp include statements
(e.g. '#include "afile.c"') to combine code from different files.
2) Compiling TAO code
To compile TAO code, the rtc compiler is used:rtc sourcefile.zzt
Remarks:
Since there is no linker available yet one has to include combine
all sources. Hint: Use include statements (e.g. '/include "afile.hzt"')
for this purpose.
3) Compiling high-level assembly
The next step is to produce the low level-assembly (masm). In this step the operating system that shall be used has to be chosen:mpp -os7 sourcefile.sasm
-os1 slow I/O via serial I2C link, stable -os3 fast I/O velocity via 7th link initiated via I2C (-> large overhead), stable -os7 fast I/O via 7th link, still being tested
-v preserve comments from sasm code
4) Assembler-level optimisation
Now the optional (but recommended) optimization is done by:sofan sourcefile.masm sourcefile-sofan.masm
Remarks:
If you don't provide the outputfile 'sourcefile-sofan.masm', the
original file will be renamed to sourcefile-nosofan.masm, and the
optimized code will be stored in 'sourcefile.masm'.
The different optimizations can be turned an/off via command line
options. See 'sofan -h' for details.
5) Microcode generation
The last step to be done is to produce the final microcode:shaker +a -z sourcefile-sofan.masm
+a Enable register allocation (mandatory for assembler generated by rtc or nlcc) -z Enable microcode compression (recommended to safe memory bandwidth when loading instructions into the processor)